Field of the Invention
This invention relates to a semiconductor device, in particular, a semiconductor device that has calibration circuit adjusting impedance of data output circuit.
Description of the Related Art
A semiconductor device such as a DRAM (Dynamic Random Access Memory) is provided with a data output circuit for outputting data to outside. The data output circuit is designed so as to obtain desired impedance when activated. However, due to the influence from process variations, temperature changes, etc., the impedance as designed is not always obtained. Therefore, in a semiconductor device in which the impedance of a data output circuit has to be controlled with high accuracy, an impedance adjustment circuit called a calibration circuit is built (see Patent Documents 1, 2).
Incidentally, recently, a semiconductor device of a type that it is divided into a plurality of channels has been proposed. The channels are circuit blocks which can be independently accessed, and each of the channels is provided with a memory cell array, an access control circuit, external terminals, etc. Basically all circuits are separated among the channels, the channels are operated in synchronization with mutually different clock signals, and mutually different external terminals are used also for reception of command/address signals and input/output of data. Thus, each of the channels can be considered as an independent single semiconductor device and, regarding this point, is distinguished from an access unit called a bank.
[Patent document 1] Japanese Laid-Open Patent Publication No. 2011-119632 (English equivalent U.S. Pat. Pub. No. 2011-0128038)
[Patent document 2] Japanese Laid-Open Patent Publication No. 2006-203405 (English equivalent U.S. Pat. Pub. No. 2006-0158198)